Modern microprocessors or integrated circuits, due to increased complexity and functionality, are requiring more clocks and cyclic control signals than their predecessors. In order to achieve multiple clocks in a microprocessor system, many microprocessors internally synthesize additional clocks from one or more system clocks that are input to the microprocessor from circuitry external to the microprocessor. A quick, inexpensive, reliable, and simple solution to the internal generation of clocks has not been achieved.
A simple approach to supplying a microprocessor with several clocks is to input several clocks into the microprocessor. This technique is not reliable and can be very expensive. The added expense is due to the fact that extra pins must be added to the microprocessor's package, and external circuitry, which may have several crystal oscillators, is required. When microprocessor operation is closely dependent on the ration of one clock frequency to another, such as in transceiver applications, data converter applications, and sample-data filter applications, this method is not adequate.
Another method is to simply divide an input system clock by a single fixed divisor using dividing circuitry. This method can only divide the system clock by a fixed value and therefore cannot be used for multiple system clock frequencies or to adapt to operational variation in system clock frequency without altering the frequency of the synthesized clock.
To improve upon the methods above, a method of using a programmable divider circuit internal to the microprocessor was adopted. User input, either through software or hardware, programs the programmable divider circuit to divide the input system clock by a specific value. This division produces an internal synthesized clock. This method requires user input and is therefore subject to error resulting from incorrect data being input by a user. This method is also not flexible because the divider cannot usually compensate itself for errors, fluctuation, or alteration in the frequency of the system clock without user intervention. An additional disadvantage is that the divider, and therefore the synthesized clock, is not functional after reset or power up until the user programs the divider.
Yet another method of supplying a microprocessor with several clocks is to store or provide internal to the microprocessor a plurality of divisors. The plurality of divisors is usually stored or provided with some indication of numerical order. The microprocessor is informed, usually through fixed hardware comparators, of a desired synthesized frequency for the synthesized clock. The hardware, upon reset, power-up or a like condition, begins to scan through all the stored or provided divisor values until one divisor produces a synthesized clock with a frequency substantially close to the desired synthesized frequency. Although this method allows for errors and alterations in the system clock, it is slow and requires a large amount of overhead in order to be accurate.
Yet another method to generate internal clocks is to use an analog phase lock loop circuit. A phase lock loop circuit uses analog circuitry and a reference clock, which is the system clock in most cases, to converge a synthesized clock value to a predetermined frequency via multiplication, division, and/or comparison. Phase lock loops, due to their analog components, are usually slow to converge, are unreliable, and are inherently unstable.